This invention relates to an electrical component package comprising a component attached to a substrate by a multisolder interconnection. More particularly, this invention relates to such interconnection comprising a spacer bump formed of a high reflow temperature solder alloy bonded to the component and set against the substrate to maintain a desired distance therebetween, and a securement portion formed of low reflow temperature solder alloy bonding the spacer bump to the substrate.
A common electrical component package comprises an electrical component mounted onto a substrate by a plurality of solder bump interconnections. Such interconnections are used, for example, for mounting a semiconductor chip onto a carrier, for mounting a chip carrier onto a printed circuit board, or for mounting a semiconductor chip directly onto a printed circuit board. In any event, the component has a generally planar interface that includes a plurality of discrete metal contacts disposed in an array or other suitable pattern. The substrate comprises a generally planar component attachment region that includes a plurality of metal contacts disposed in a pattern corresponding to the component contacts. With the component interface overlaying the substrate region, each component contact is individually connected to the corresponding substrate contact by a solder bump interconnection. A common method for forming a solder bump interconnection utilizes a microball composed of tin-lead solder alloy. The microball is placed onto the component contact, heated and cooled to reflow the alloy to form a bump and to bond the bump to the contact. The component is then assembled with the substrate so that the bump rests upon the corresponding substrate contact. The assembly is heated and cooled to bond the bump to the substrate contact. This attaches the component to the substrate and electrically connects the contacts for conducting electrical signals therebetween, with the component interface and the substrate region spaced apart by the solder bump.
The components and the substrate are generally formed of different materials. For example, the component may be a silicon chip or an alumina chip carrier, whereas the substrate may be a printed circuit board formed of a glass fiber-reinforced epoxy resin. These materials have significantly different coefficients of thermal expansion. During thermal cycling such as typically experienced by the package during operation, the component and the substrate tend to expand and contract, but at different rates. This mismatch creates stresses that tend to produce fatigue within the solder bonds and may result in catastrophic failure of the interconnection. It is desired to utilize a solder alloy having a high lead content, preferably greater than 90 percent, to produce a strong bond that resists thermal fatigue. However, high-lead solder alloys require reflow temperatures sufficient to cause thermal degradation of epoxy resin and are thus not suitable for printed circuit board substrates.
Also, during reflow on the substrate, the solder bump tends to collapse under the weight of the component, creating a pancake configuration that tends to concentrate the thermal fatigue stresses at the solder bonds. It has been proposed to form an interconnection having an hour glass configuration to distribute the thermal fatigue stresses and thereby extend the useful life of the electrical component package. Furthermore, collapse of the solder bumps during assembly reduces the component-substrate gap and thereby restricts access for solvent cleaning or other post-interconnection operations.